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powerpc: use more target-independent llvm intrinsics (min, max, round, countlz) #1713

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Merged
merged 5 commits into from
Feb 23, 2025
Merged

powerpc: use more target-independent llvm intrinsics (min, max, round, countlz) #1713

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b08a73e
use generic llvm intrinsics for min/max on powerpc
folkertdev Feb 13, 2025
1694df9
use `llvm.nearbyint.v4f32` for rounding
folkertdev Feb 13, 2025
752d0ce
use `simd_ctlz` instead of an extern
folkertdev Feb 13, 2025
9a1cbcd
use `simd_shuffle` in the implementation of `vec_splat`
folkertdev Feb 22, 2025
aaa01da
use `simd_neg` in the `impl crate::ops::Neg`
folkertdev Feb 22, 2025
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39 changes: 16 additions & 23 deletions crates/core_arch/src/powerpc/altivec.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -158,32 +158,32 @@ unsafe extern "C" {
#[link_name = "llvm.ppc.altivec.vmulosh"]
fn vmulosh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_int;

#[link_name = "llvm.ppc.altivec.vmaxsb"]
#[link_name = "llvm.smax.v16i8"]
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Since these are generic LLVM vector intrinsics, it would make more sense to provide these in core::intrinsics::simd and then use them from stdarch, similar to how simd_neg is used.

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I see this is already a pattern in quite a few places in stdarch. This doesn't need to block this PR, it can be resolved separately.

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yeah, makes sense. I'll add that then.

fn vmaxsb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char;
#[link_name = "llvm.ppc.altivec.vmaxsh"]
#[link_name = "llvm.smax.v8i16"]
fn vmaxsh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short;
#[link_name = "llvm.ppc.altivec.vmaxsw"]
#[link_name = "llvm.smax.v4i32"]
fn vmaxsw(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;

#[link_name = "llvm.ppc.altivec.vmaxub"]
#[link_name = "llvm.umax.v16i8"]
fn vmaxub(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char;
#[link_name = "llvm.ppc.altivec.vmaxuh"]
#[link_name = "llvm.umax.v8i16"]
fn vmaxuh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short;
#[link_name = "llvm.ppc.altivec.vmaxuw"]
#[link_name = "llvm.umax.v4i32"]
fn vmaxuw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int;

#[link_name = "llvm.ppc.altivec.vminsb"]
#[link_name = "llvm.smin.v16i8"]
fn vminsb(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char;
#[link_name = "llvm.ppc.altivec.vminsh"]
#[link_name = "llvm.smin.v8i16"]
fn vminsh(a: vector_signed_short, b: vector_signed_short) -> vector_signed_short;
#[link_name = "llvm.ppc.altivec.vminsw"]
#[link_name = "llvm.smin.v4i32"]
fn vminsw(a: vector_signed_int, b: vector_signed_int) -> vector_signed_int;

#[link_name = "llvm.ppc.altivec.vminub"]
#[link_name = "llvm.umin.v16i8"]
fn vminub(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char;
#[link_name = "llvm.ppc.altivec.vminuh"]
#[link_name = "llvm.umin.v8i16"]
fn vminuh(a: vector_unsigned_short, b: vector_unsigned_short) -> vector_unsigned_short;
#[link_name = "llvm.ppc.altivec.vminuw"]
#[link_name = "llvm.umin.v4i32"]
fn vminuw(a: vector_unsigned_int, b: vector_unsigned_int) -> vector_unsigned_int;

#[link_name = "llvm.ppc.altivec.vsubsbs"]
Expand Down Expand Up @@ -368,21 +368,14 @@ unsafe extern "C" {
#[link_name = "llvm.ppc.altivec.srv"]
fn vsrv(a: vector_unsigned_char, b: vector_unsigned_char) -> vector_unsigned_char;

#[link_name = "llvm.ctlz.v16i8"]
fn vclzb(a: vector_signed_char) -> vector_signed_char;
#[link_name = "llvm.ctlz.v8i16"]
fn vclzh(a: vector_signed_short) -> vector_signed_short;
#[link_name = "llvm.ctlz.v4i32"]
fn vclzw(a: vector_signed_int) -> vector_signed_int;

#[link_name = "llvm.ppc.altivec.vrlb"]
fn vrlb(a: vector_signed_char, b: vector_unsigned_char) -> vector_signed_char;
#[link_name = "llvm.ppc.altivec.vrlh"]
fn vrlh(a: vector_signed_short, b: vector_unsigned_short) -> vector_signed_short;
#[link_name = "llvm.ppc.altivec.vrlw"]
fn vrlw(a: vector_signed_int, c: vector_unsigned_int) -> vector_signed_int;

#[link_name = "llvm.ppc.altivec.vrfin"]
#[link_name = "llvm.nearbyint.v4f32"]
fn vrfin(a: vector_float) -> vector_float;
Comment on lines -385 to 379
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I've verified that these in fact produce identical assembly https://godbolt.org/z/Wx1KWezbe

}

Expand Down Expand Up @@ -3191,9 +3184,9 @@ mod sealed {

impl_vec_shift_octect! { [VectorSro vec_sro] (vsro) }

test_impl! { vec_vcntlzb(a: vector_signed_char) -> vector_signed_char [vclzb, vclzb] }
test_impl! { vec_vcntlzh(a: vector_signed_short) -> vector_signed_short [vclzh, vclzh] }
test_impl! { vec_vcntlzw(a: vector_signed_int) -> vector_signed_int [vclzw, vclzw] }
test_impl! { vec_vcntlzb(a: vector_signed_char) -> vector_signed_char [simd_ctlz, vclzb] }
test_impl! { vec_vcntlzh(a: vector_signed_short) -> vector_signed_short [simd_ctlz, vclzh] }
test_impl! { vec_vcntlzw(a: vector_signed_int) -> vector_signed_int [simd_ctlz, vclzw] }

#[unstable(feature = "stdarch_powerpc", issue = "111145")]
pub trait VectorCntlz {
Expand Down