[RISC-V] Introduce C extension for Integer Register-Register Operations #117408

fuad1502 · 2025-07-08T06:34:20Z

This is a first attempt at utilizing the C extension for the RISC-V JIT compiler.

Here's what's changed in this PR:

Use compressed instructions for integer register-register operations whenever possible ("The RISC-V Instruction Set Manual Volume I", Chapter 27.5.3)
Reduce code alignment down to 2 bytes
Adjust unwind info & unwinder to work with the new code alignment.
Match RISC-V R2RDump format with other architecture with variable length instructions (Arm32 / XArch)
Temporarily disable ProbeRiscV64Quirks in R2RDump

This PR does not fully utilize the C extension yet. Here are some things that must be addressed in a follow up PR:

Introduce C extension for other operations (load and store instructions, integer constant-generation instructions, and integer register-immediate operations)
Use compressed instructions inside prolog & epilog and update the prolog length computation from unwind codes (refer to ARM32 implementation).
Modify ProbeRiscV64Quirks in R2RDump to detect patterns by forward traversing, similar to Arm64 implementation`.

R2RDump sample output:

public static long FunAdd(long a, long b)
{
        return a + b;
}

long Program.FunAdd(long, long)
Handle: 0x06000002
Rid: 2
EntryPointRuntimeFunctionId: 1
Number of RuntimeFunctions: 1

long Program.FunAdd(long, long)
Id: 1
StartAddress: 0x00010BD0
Size: 34 bytes
UnwindRVA: 0x0001091C

Debug Info
    Bounds:
    Native Offset: 0x0, Prolog, Source Types: StackEmpty
    Native Offset: 0x10, IL Offset: 0x0000, Source Types: StackEmpty
    Native Offset: 0x12, Epilog, Source Types: StackEmpty

    Variable Locations:
    Variable Number: 0
    Start Offset: 0x0
    End Offset: 0x10
    Loc Type: VLT_REG
    Register: A0

    Variable Number: 1
    Start Offset: 0x0
    End Offset: 0x10
    Loc Type: VLT_REG
    Register: A1

10bd0: 13 01 01 ff     addi    sp, sp, -16
10bd4: 23 30 81 00     sd      s0, 0(sp)
10bd8: 23 34 11 00     sd      ra, 8(sp)
10bdc: 13 04 01 00     mv      s0, sp
10be0: 2e 95           add     a0, a0, a1 ;; RVC instruction
10be2: 83 30 81 00     ld      ra, 8(sp)
10be6: 03 34 01 00     ld      s0, 0(sp)
10bea: 13 01 01 01     addi    sp, sp, 16
10bee: 67 80 00 00     ret

Part of #84834, cc @dotnet/samsung

fuad1502 · 2025-07-08T06:35:59Z

Diffs are based on 13,180 contexts (10,390 MinOpts, 2,790 FullOpts).

Overall (-12,754 bytes)

Collection	Base size (bytes)	Diff size (bytes)	PerfScore in Diffs
test.mch	6,484,408	-12,754	-0.00%

MinOpts (-7,098 bytes)

Collection	Base size (bytes)	Diff size (bytes)	PerfScore in Diffs
test.mch	4,707,060	-7,098	-0.00%

FullOpts (-5,656 bytes)

Collection	Base size (bytes)	Diff size (bytes)	PerfScore in Diffs
test.mch	1,777,348	-5,656	-0.00%

Example diffs

test.mch

-4 (-8.33%) : 7688.dasm - Microsoft.CodeAnalysis.CSharp.BinderFlagsExtensions:Includes(uint,uint):bool (Tier1)

@@ -27,14 +27,14 @@ G_M26379_IG02:        ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
             sext.w         a0, a0
             subw           a0, a0, a1
             sltiu          a0, a0, 1
-						;; size=16 bbWeight=1 PerfScore 2.00
+						;; size=12 bbWeight=1 PerfScore 2.00
 G_M26379_IG03:        ; bbWeight=1, epilog, nogc, extend
             ld             ra, 8(sp)
             ld             fp, 0(sp)
             addi           sp, sp, 16
             ret						;; size=16 bbWeight=1 PerfScore 7.50
 
-; Total bytes of code 48, prolog size 16, PerfScore 18.50, instruction count 12, allocated bytes for code 48 (MethodHash=815098f4) for method Microsoft.CodeAnalysis.CSharp.BinderFlagsExtensions:Includes(uint,uint):bool (Tier1)
+; Total bytes of code 44, prolog size 16, PerfScore 18.50, instruction count 12, allocated bytes for code 44 (MethodHash=815098f4) for method Microsoft.CodeAnalysis.CSharp.BinderFlagsExtensions:Includes(uint,uint):bool (Tier1)
 ; ============================================================
 
 Unwind Info:
@@ -45,7 +45,7 @@ Unwind Info:
   E bit             : 0
   X bit             : 0
   Vers              : 0
-  Function Length   : 12 (0x0000c) Actual length = 48 (0x000030)
+  Function Length   : 22 (0x00016) Actual length = 44 (0x00002c)
   ---- Epilog scopes ----
   ---- Scope 0
   Epilog Start Offset        : 3523193630 (0xd1ffab1e) Actual offset = 3523193630 (0xd1ffab1e) Offset from main function begin = 3523193630 (0xd1ffab1e)

-8 (-8.00%) : 3238.dasm - Microsoft.CodeAnalysis.CachingBase`1[System.__Canon]:AlignSize(int):int (Tier1)

@@ -40,14 +40,14 @@ G_M65205_IG02:        ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
             or             a0, a1, a0
             sext.w         a0, a0
             addiw          a0, a0, 0xD1FFAB1E
-						;; size=68 bbWeight=1 PerfScore 8.50
+						;; size=60 bbWeight=1 PerfScore 8.50
 G_M65205_IG03:        ; bbWeight=1, epilog, nogc, extend
             ld             ra, 8(sp)
             ld             fp, 0(sp)
             addi           sp, sp, 16
             ret						;; size=16 bbWeight=1 PerfScore 7.50
 
-; Total bytes of code 100, prolog size 16, PerfScore 25.00, instruction count 25, allocated bytes for code 100 (MethodHash=8bf1014a) for method Microsoft.CodeAnalysis.CachingBase`1[System.__Canon]:AlignSize(int):int (Tier1)
+; Total bytes of code 92, prolog size 16, PerfScore 25.00, instruction count 25, allocated bytes for code 92 (MethodHash=8bf1014a) for method Microsoft.CodeAnalysis.CachingBase`1[System.__Canon]:AlignSize(int):int (Tier1)
 ; ============================================================
 
 Unwind Info:
@@ -58,7 +58,7 @@ Unwind Info:
   E bit             : 0
   X bit             : 0
   Vers              : 0
-  Function Length   : 25 (0x00019) Actual length = 100 (0x000064)
+  Function Length   : 46 (0x0002e) Actual length = 92 (0x00005c)
   ---- Epilog scopes ----
   ---- Scope 0
   Epilog Start Offset        : 3523193630 (0xd1ffab1e) Actual offset = 3523193630 (0xd1ffab1e) Offset from main function begin = 3523193630 (0xd1ffab1e)

-14 (-7.29%) : 4638.dasm - System.Reflection.RuntimeMethodInfo:GetHashCode():int:this (Instrumented Tier1)

@@ -83,14 +83,14 @@ G_M36882_IG02:        ; bbWeight=1, gcrefRegs=0400 {a0}, byrefRegs=0000 {}, byre
             srliw          a1, a0, 16
             xor            a0, a0, a1
             sext.w         a0, a0
-						;; size=160 bbWeight=1 PerfScore 38.50
+						;; size=146 bbWeight=1 PerfScore 38.50
 G_M36882_IG03:        ; bbWeight=1, epilog, nogc, extend
             ld             ra, 8(sp)
             ld             fp, 0(sp)
             addi           sp, sp, 16
             ret						;; size=16 bbWeight=1 PerfScore 7.50
 
-; Total bytes of code 192, prolog size 16, PerfScore 55.00, instruction count 43, allocated bytes for code 192 (MethodHash=8fbf6fed) for method System.Reflection.RuntimeMethodInfo:GetHashCode():int:this (Instrumented Tier1)
+; Total bytes of code 178, prolog size 16, PerfScore 55.00, instruction count 43, allocated bytes for code 178 (MethodHash=8fbf6fed) for method System.Reflection.RuntimeMethodInfo:GetHashCode():int:this (Instrumented Tier1)
 ; ============================================================
 
 Unwind Info:
@@ -101,7 +101,7 @@ Unwind Info:
   E bit             : 0
   X bit             : 0
   Vers              : 0
-  Function Length   : 48 (0x00030) Actual length = 192 (0x0000c0)
+  Function Length   : 89 (0x00059) Actual length = 178 (0x0000b2)
   ---- Epilog scopes ----
   ---- Scope 0
   Epilog Start Offset        : 3523193630 (0xd1ffab1e) Actual offset = 3523193630 (0xd1ffab1e) Offset from main function begin = 3523193630 (0xd1ffab1e)

+0 (0.00%) : 13168.dasm - LUDecomp:lusolve(double[][],int,double[]):int (Instrumented Tier0)

@@ -114,7 +114,7 @@ Unwind Info:
   E bit             : 0
   X bit             : 0
   Vers              : 0
-  Function Length   : 71 (0x00047) Actual length = 284 (0x00011c)
+  Function Length   : 142 (0x0008e) Actual length = 284 (0x00011c)
   ---- Epilog scopes ----
   ---- Scope 0
   Epilog Start Offset        : 3523193630 (0xd1ffab1e) Actual offset = 3523193630 (0xd1ffab1e) Offset from main function begin = 3523193630 (0xd1ffab1e)

+0 (0.00%) : 13152.dasm - Neural:DoNNetIteration(long):long (Tier1)

@@ -271,7 +271,7 @@ Unwind Info:
   E bit             : 0
   X bit             : 0
   Vers              : 0
-  Function Length   : 213 (0x000d5) Actual length = 852 (0x000354)
+  Function Length   : 426 (0x001aa) Actual length = 852 (0x000354)
   ---- Epilog scopes ----
   ---- Scope 0
   Epilog Start Offset        : 3523193630 (0xd1ffab1e) Actual offset = 3523193630 (0xd1ffab1e) Offset from main function begin = 3523193630 (0xd1ffab1e)

+0 (0.00%) : 13120.dasm - Neural:do_out_error(int) (Instrumented Tier0)

@@ -284,7 +284,7 @@ Unwind Info:
   E bit             : 0
   X bit             : 0
   Vers              : 0
-  Function Length   : 210 (0x000d2) Actual length = 840 (0x000348)
+  Function Length   : 420 (0x001a4) Actual length = 840 (0x000348)
   ---- Epilog scopes ----
   ---- Scope 0
   Epilog Start Offset        : 3523193630 (0xd1ffab1e) Actual offset = 3523193630 (0xd1ffab1e) Offset from main function begin = 3523193630 (0xd1ffab1e)

Details

Size improvements/regressions per collection

Collection	Contexts with diffs	Improvements	Regressions	Same size	Improvements (bytes)	Regressions (bytes)
test.mch	13,180	2,191	0	10,989	-12,754	+0

PerfScore improvements/regressions per collection

Collection	Contexts with diffs	Improvements	Regressions	Same PerfScore	Improvements (PerfScore)	Regressions (PerfScore)	PerfScore Overall in FullOpts
test.mch	13,180	4	0	13,176	-1.05%	0.00%	-0.0014%

Context information

Collection	Diffed contexts	MinOpts	FullOpts	Missed, base	Missed, diff
test.mch	13,180	10,390	2,790	0 (0.00%)	0 (0.00%)

jit-analyze output

risc-vv · 2025-07-08T08:43:58Z

RISC-V Release-CLR-QEMU: 9041 / 9092 (99.44%)

=======================
      passed: 9041
      failed: 23
     skipped: 599
      killed: 28
------------------------
 TOTAL tests: 9691
VIRTUAL time: 35h 15min 16s 855ms
   REAL time: 1h 9min 50s 641ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

RISC-V Release-FX-QEMU: 9146 / 9251 (98.86%)

=======================
      passed: 9146
      failed: 3
     skipped: 39
      killed: 102
------------------------
 TOTAL tests: 9290
VIRTUAL time: 3h 51min 9s 692ms
   REAL time: 1h 33min 2s 195ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

RISC-V Release-CLR-VF2: 9036 / 9090 (99.41%)

=======================
      passed: 9036
      failed: 25
     skipped: 599
      killed: 29
------------------------
 TOTAL tests: 9689
VIRTUAL time: 10h 30min 19s 493ms
   REAL time: 2h 22min 47s 689ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

RISC-V Release-FX-VF2: 4322 / 4437 (97.41%)

=======================
      passed: 4322
      failed: 3
     skipped: 39
      killed: 112
------------------------
 TOTAL tests: 4476
VIRTUAL time: 1h 32min 57s 990ms
   REAL time: 6h 5min 2s 118ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

Build information and commands

GIT: 654c6ae7744fc436570702a9bc9cba6f75e1aea4
CI: 78e142fd33020d1c98d51294d2e82d7c5be9fbf2
REPO: dotnet/runtime
BRANCH: main
CONFIG: Release
LIB_CONFIG: Release

src/coreclr/jit/emitriscv64.cpp

tomeksowi · 2025-07-08T10:38:34Z

You also may want to see if R2RDump works with the new formats, there may be some silent assumptions about instruction width in e.g. ProbeRiscV64Quirks

src/coreclr/jit/emitriscv64.cpp

Co-authored-by: Tomasz Sowiński <[email protected]>

risc-vv · 2025-07-08T10:51:22Z

RISC-V Release-FX-QEMU: 8632 / 8737 (98.80%)

=======================
      passed: 8632
      failed: 5
     skipped: 39
      killed: 100
------------------------
 TOTAL tests: 8776
VIRTUAL time: 3h 53min 12s 300ms
   REAL time: 1h 33min 6s 46ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

RISC-V Release-CLR-VF2: 9035 / 9090 (99.39%)

=======================
      passed: 9035
      failed: 26
     skipped: 599
      killed: 29
------------------------
 TOTAL tests: 9689
VIRTUAL time: 9h 39min 17s 204ms
   REAL time: 2h 20min 6s 249ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

RISC-V Release-CLR-QEMU: 9042 / 9093 (99.44%)

=======================
      passed: 9042
      failed: 23
     skipped: 599
      killed: 28
------------------------
 TOTAL tests: 9692
VIRTUAL time: 36h 27min 10s 644ms
   REAL time: 1h 9min 56s 640ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

Build information and commands

GIT: 2aa771773e517d8eee7d9e935cf5ad12fb7d7204
CI: 78e142fd33020d1c98d51294d2e82d7c5be9fbf2
REPO: dotnet/runtime
BRANCH: main
CONFIG: Release
LIB_CONFIG: Release

src/coreclr/jit/emitriscv64.cpp

…neration Co-authored-by: Tomasz Sowiński <[email protected]>

am11 · 2025-07-08T11:45:32Z

ILC: /__w/1/s/src/coreclr/jit/emitriscv64.cpp:997
ILC: Assertion failed '!emitComp->compGeneratingProlog && !emitComp->compGeneratingEpilog' in 'System.Math:Round(double):double' during 'Generate code' (IL size 47; hash 0x4926443d; FullOpts)

This error seems related. ☝️

src/coreclr/jit/emitriscv64.cpp

fuad1502 · 2025-07-08T12:12:11Z

Thanks for reviewing! @tomeksowi @am11 @sirntar

After the reviews, I can see many things aren't quite right yet in this PR:

Need to check places related with idAddr()->iiaHasInstrCount
Need to check R2RDump
Need to make sure compressed instructions are not yet used in prolog / epilog

For now, I'll mark this PR as a draft again, make the necessary changes and I'll try to test the CLR tests locally first before pushing 👍

But feel free to keep reviewing and please let me know if there's anything I might've missed! Thanks everyone 😃

fuad1502 · 2025-07-08T14:51:56Z

Hi @sirntar , somehow the CI is triggered for the same commit multiple times 😅 Can you please help check when you have the time? Thank you very much 🙏

Sorry if it is somehow caused by build failure. In the meantime, I'll push a quick fix patch just in case 🙏

Edit: already pushed temporary "fix" for build error on 270a63d

…enerate compressed instruction in prolog / epilog

risc-vv · 2025-07-08T15:16:37Z

RISC-V Release-CLR-VF2: 9036 / 9089 (99.42%)

=======================
      passed: 9036
      failed: 24
     skipped: 600
      killed: 29
------------------------
 TOTAL tests: 9689
VIRTUAL time: 9h 53min 53s 229ms
   REAL time: 2h 21min 23s 250ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

RISC-V Release-CLR-QEMU: 9041 / 9094 (99.42%)

=======================
      passed: 9041
      failed: 25
     skipped: 600
      killed: 28
------------------------
 TOTAL tests: 9694
VIRTUAL time: 36h 22min 29s 131ms
   REAL time: 1h 8min 49s 773ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

Build information and commands

GIT: 270a63dbf554c1b85482bfbbe04eda53a8a0c741
CI: 78e142fd33020d1c98d51294d2e82d7c5be9fbf2
REPO: fuad1502/runtime
BRANCH: riscv-jit-opt/c-ext
CONFIG: Release
LIB_CONFIG: Release

risc-vv · 2025-07-08T16:11:14Z

RISC-V Release-FX-QEMU: 9046 / 9154 (98.82%)

=======================
      passed: 9046
      failed: 4
     skipped: 39
      killed: 104
------------------------
 TOTAL tests: 9193
VIRTUAL time: 4h 8min 25s 614ms
   REAL time: 1h 32min 18s 894ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

RISC-V Release-FX-VF2: 5993 / 6108 (98.12%)

=======================
      passed: 5993
      failed: 5
     skipped: 38
      killed: 110
------------------------
 TOTAL tests: 6146
VIRTUAL time: 1h 52min 30s 949ms
   REAL time: 6h 5min 29s 796ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

Build information and commands

GIT: 270a63dbf554c1b85482bfbbe04eda53a8a0c741
CI: 78e142fd33020d1c98d51294d2e82d7c5be9fbf2
REPO: fuad1502/runtime
BRANCH: riscv-jit-opt/c-ext
CONFIG: Release
LIB_CONFIG: Release

src/coreclr/jit/emitriscv64.cpp

tomeksowi · 2025-07-08T17:06:43Z

Something to watch out for: hardcoded branch offsets, e.g. here:

runtime/src/coreclr/jit/codegenriscv64.cpp

Lines 1605 to 1609 in 6d869a8

    
           // tickle the page - this triggers a page fault when on the guard page 
        
           emit->emitIns_R_R_I(INS_lw, EA_4BYTE, REG_R0, tempReg, 0); 
        
           emit->emitIns_R_R_R(INS_sub, EA_4BYTE, tempReg, tempReg, rPageSize); 
        
           emit->emitIns_R_R_I(INS_bgeu, EA_PTRSIZE, tempReg, regCnt, -2 << 2);

Is there anything preventing allocating the temps in a way to allow sub to compress?

We have them in a couple of places, they may become pain spots as we add support for more compressed instructions, there's nothing checking if the offset matches the intended target.

fuad1502 · 2025-07-09T07:15:57Z

I've went through the code to understand the issue raised by @tomeksowi. From what I understand, at some places we use emitIns_R_R_I(INS_b*, ..., instrCount * 4) to conditionally jump around instrCount instructions. And inside emitIns_R_R_I, we also call iiaSetInstrCount with offset / 4. These assumptions may not hold anymore since some instructions are compressed.

To fix this issue, I propose three alternative solutions:

The long term approach:
- Correctly use instrCount parameter in emitIns_J to allow substitution with emitIns_J, e.g. emitIns_R_R_I(..., instrCount * 4) becomes emitIns_J(..., instrCount). Currently, instrCount is used to pass reg1 and reg2.
- Use emitIns_J and emitIns_J_cond_la for all jump and branch instructions, unless we know the number of offset bytes.
- Remove iiaSetInstrCount in emitIns_R_R_R(INS_b*, ...).
Quick fix approaches:
- Approach 1:
  - Introduce an emit attribute to disable compressed instruction. For example, when we want to use emitIns_R_R_I(..., instrCount * 4), we can set the attribute on the instrutions we wish to jump around.
- Approach 2:
  - Add bool *wasCompressed = NULL parameter to emitIns_R_* to allow callers to know the number of bytes emitted, and therefore also know the immediate value to supply to branching instructions.
  - Remove iiaSetInstrCount in emitIns_R_R_R(INS_b*, ...).
- Approach 3:
  - Add new public emitter methods, emitIns_*_NoCompress.

Alternative 1 should probably be done in a separate PR. While the quick fixes can be easily incorporated to this PR.

Any thoughts? Please let me know if I there's anything I misunderstood 🙏

tomeksowi · 2025-07-09T12:14:06Z

To fix this issue, I propose three alternative solutions:

Maybe just convert to branches with labels? e.g. here:

runtime/src/coreclr/jit/codegenriscv64.cpp

Lines 2324 to 2336 in 513ff1a

    
           BasicBlock* retry = genCreateTempLabel(); 
        
           BasicBlock* fail  = genCreateTempLabel(); 
        
           emitter* e    = GetEmitter(); 
        
           emitAttr size = emitActualTypeSize(valOp); 
        
           bool     is4  = (size == EA_4BYTE); 
        
           genDefineTempLabel(retry); 
        
           e->emitIns_R_R_R(is4 ? INS_lr_w : INS_lr_d, size, target, loc, REG_R0); // load original value 
        
           e->emitIns_J_cond_la(INS_bne, fail, target, comparand);                 // fail if doesn’t match 
        
           e->emitIns_R_R_R(is4 ? INS_sc_w : INS_sc_d, size, storeErr, loc, val);  // try to update 
        
           e->emitIns_J(INS_bnez, retry, storeErr);                                // retry if update failed 
        
           genDefineTempLabel(fail);

IMO it's acceptable to sacrifice through-put a little to get a safe "C" implementation going.

risc-vv · 2025-07-16T06:37:09Z

RISC-V Release-CLR-QEMU: 9085 / 9116 (99.66%)

=======================
      passed: 9085
      failed: 3
     skipped: 597
      killed: 28
------------------------
 TOTAL tests: 9713
VIRTUAL time: 37h 32min 13s 365ms
   REAL time: 38min 16s 162ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

RISC-V Release-CLR-VF2: 9085 / 9116 (99.66%)

=======================
      passed: 9085
      failed: 3
     skipped: 597
      killed: 28
------------------------
 TOTAL tests: 9713
VIRTUAL time: 12h 19min 4s 770ms
   REAL time: 49min 35s 556ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

RISC-V Release-FX-QEMU: 283563 / 284649 (99.62%)

=======================
      passed: 283563
      failed: 1077
     skipped: 39
      killed: 9
------------------------
 TOTAL tests: 284688
VIRTUAL time: 32h 29min 50s 252ms
   REAL time: 1h 11min 29s 230ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

RISC-V Release-FX-VF2: 270226 / 271908 (99.38%)

=======================
      passed: 270226
      failed: 1663
     skipped: 39
      killed: 19
------------------------
 TOTAL tests: 271947
VIRTUAL time: 20h 28min 47s 272ms
   REAL time: 2h 0min 42s 748ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

Build information and commands

GIT: 324258bc9ec1f95a75a751aeaf801a950fe52a58
CI: d6c9c1ab3a7411819463edc05ded301e89ba586a
REPO: dotnet/runtime
BRANCH: main
CONFIG: Release
LIB_CONFIG: Release

… c.* prefix in RVC instruction names

src/coreclr/debug/di/module.cpp

src/coreclr/tools/r2rdump/CoreDisTools.cs

Co-authored-by: Tomasz Sowiński <[email protected]>

risc-vv · 2025-07-17T06:53:20Z

RISC-V Release-CLR-QEMU: 9087 / 9117 (99.67%)

=======================
      passed: 9087
      failed: 2
     skipped: 597
      killed: 28
------------------------
 TOTAL tests: 9714
VIRTUAL time: 37h 21min 59s 682ms
   REAL time: 38min 5s 5ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

RISC-V Release-CLR-VF2: 9088 / 9118 (99.67%)

=======================
      passed: 9088
      failed: 2
     skipped: 597
      killed: 28
------------------------
 TOTAL tests: 9715
VIRTUAL time: 12h 2min 42s 708ms
   REAL time: 48min 37s 520ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

RISC-V Release-FX-QEMU: 285333 / 286424 (99.62%)

=======================
      passed: 285333
      failed: 1084
     skipped: 39
      killed: 7
------------------------
 TOTAL tests: 286463
VIRTUAL time: 31h 34min 20s 336ms
   REAL time: 1h 11min 30s 862ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

RISC-V Release-FX-VF2: 250861 / 252567 (99.32%)

=======================
      passed: 250861
      failed: 1685
     skipped: 39
      killed: 21
------------------------
 TOTAL tests: 252606
VIRTUAL time: 21h 34min 20s 126ms
   REAL time: 2h 7min 31s 215ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

Build information and commands

GIT: aa169fe6cd88206473cab447de55a747e83e7cd2
CI: d6c9c1ab3a7411819463edc05ded301e89ba586a
REPO: dotnet/runtime
BRANCH: main
CONFIG: Release
LIB_CONFIG: Release

fuad1502 · 2025-07-24T03:45:25Z

Hi @jakobbotsch @MichalStrehovsky can you help review this PR once you're available? Thank you 🙂🙏

JulieLeeMSFT · 2025-08-18T17:41:04Z

Hi @jakobbotsch @MichalStrehovsky can you help review this PR once you're available? Thank you 🙂🙏

@jakobbotsch @MichalStrehovsky, pinging again for code review. Thanks!

MichalStrehovsky · 2025-08-19T05:14:27Z

@jakobbotsch @MichalStrehovsky, pinging again for code review. Thanks!

I don't see anything I could review. The change in TargetDetails.cs LGTM provided RISC-V requires methods to be aligned at 2 byte boundary. The change in ElfObjectWriter.cs LGTM provided the code that is generated matches the ELF ABI specified there. These are all codegen questions.

src/coreclr/jit/unwind.h

jakobbotsch · 2025-08-19T16:07:21Z

Can you please resolve the conflicts?

fuad1502 · 2025-08-20T00:11:50Z

@risc-vv /run

risc-vv · 2025-08-20T00:16:16Z

RISC-V pull_request-CLR-QEMU: 9106 / 9136 (99.67%)

=======================
      passed: 9106
      failed: 2
     skipped: 586
      killed: 28
------------------------
 TOTAL tests: 9722
VIRTUAL time: 80h 18min 27s 290ms
   REAL time: 1h 19min 35s 765ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

RISC-V pull_request-CLR-VF2: 9107 / 9137 (99.67%)

=======================
      passed: 9107
      failed: 2
     skipped: 586
      killed: 28
------------------------
 TOTAL tests: 9723
VIRTUAL time: 32h 38min 35s 593ms
   REAL time: 2h 9min 37s 203ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

RISC-V pull_request-FX-QEMU: 0 / 0 (100.00%)

=======================
      passed: 0
      failed: 0
     skipped: 14
      killed: 0
------------------------
 TOTAL tests: 14
VIRTUAL time: 0ms
   REAL time: 4h 30min 0s 532ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

RISC-V pull_request-FX-VF2: 0 / 52 (0.00%)

=======================
      passed: 0
      failed: 0
     skipped: 14
      killed: 52
------------------------
 TOTAL tests: 66
VIRTUAL time: 1min 4s 582ms
   REAL time: 13h 30min 6s 239ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

Build information and commands

GIT: c011705986e4ea307737c4f4e0db775fe0984a0d
CI: d023c7d591ab286aa343d644f00b5daa59d8d6b0
REPO: dotnet/runtime
BRANCH: main
CONFIG: Checked
LIB_CONFIG: Release

We're introducing RVC instructions to RISC-V JIT in dotnet/runtime: dotnet/runtime#117408 With that PR and this PR, output of `R2RDump` tool for the following C# method: ```cs public static long FunAdd(long a, long b) { return a + b; } ``` is as follows: ```asm long Program.FunAdd(long, long) Handle: 0x06000002 Rid: 2 EntryPointRuntimeFunctionId: 1 Number of RuntimeFunctions: 1 long Program.FunAdd(long, long) Id: 1 StartAddress: 0x00010BD0 Size: 34 bytes UnwindRVA: 0x0001091C Debug Info Bounds: Native Offset: 0x0, Prolog, Source Types: StackEmpty Native Offset: 0x10, IL Offset: 0x0000, Source Types: StackEmpty Native Offset: 0x12, Epilog, Source Types: StackEmpty Variable Locations: Variable Number: 0 Start Offset: 0x0 End Offset: 0x10 Loc Type: VLT_REG Register: A0 Variable Number: 1 Start Offset: 0x0 End Offset: 0x10 Loc Type: VLT_REG Register: A1 10bd0: 13 01 01 ff addi sp, sp, -16 10bd4: 23 30 81 00 sd s0, 0(sp) 10bd8: 23 34 11 00 sd ra, 8(sp) 10bdc: 13 04 01 00 mv s0, sp 10be0: 2e 95 add a0, a0, a1 ;; RVC instruction 10be2: 83 30 81 00 ld ra, 8(sp) 10be6: 03 34 01 00 ld s0, 0(sp) 10bea: 13 01 01 01 addi sp, sp, 16 10bee: 67 80 00 00 ret ```

fuad1502 added 2 commits July 7, 2025 23:42

Introduce C extension; decrease code alignment to 2 bytes

c6832e1

Utilize C extension for the rest of integer register-register operations

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slow macOS - "##[error]The job running on agent Azure Pipelines 9 ran longer than the maximum time of 60 minutes." dotnet/dnceng#1883

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The Operation will be canceled. The next steps may not contain expected logs. dotnet/dnceng#3008

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Ensure compressed instructions are not yet used in prolog / epilog ge…

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browser-wasm Windows build error #116746

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am11 added the arch-riscv Related to the RISC-V architecture label Jul 8, 2025

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Temporarily disable assertion & return early instead when trying to g…

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…enerate compressed instruction in prolog / epilog

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Fix missed adjustments to unwind info

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fuad1502 added 2 commits July 16, 2025 14:49

Merge branch 'main' into riscv-jit-opt/c-ext

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Add TODO comment on introducing a switch in jitconfigvalues.h to show…

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… c.* prefix in RVC instruction names

fuad1502 marked this pull request as ready for review July 16, 2025 07:56

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X509Certificates.Tests.ChainTests.BuildChainCustomTrustStore failure on linux musl #117723

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System.Security.Cryptography.X509Certificates.Tests fails on linux #117724

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Fix if defined guard usage

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System.ComponentModel.Win32Exception : An error occurred trying to start process 'notepad.exe' with working directory 'C:\h\w\9F8D0903\w\B7E309C0\e'. Access is denied #90406

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Temporarily disable ProbeRiscV64Quirks

3aed899

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System.Diagnostics.Tests.ProcessTests.TestCheckChildProcessUserAndGroupIds fails on Alpine jobs with "Operation not permitted" #117811

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Merge branch 'main' into riscv-jit-opt/c-ext

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System.Data.OleDb.Tests timeout in net48 x86 Release leg #87783

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jakobbotsch merged commit 688beda into dotnet:main Aug 20, 2025
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[RISC-V] R2RDump: revamp probing quirks #118980

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[RISC-V] Introduce C extension for Integer Register-Register Operations #117408

[RISC-V] Introduce C extension for Integer Register-Register Operations #117408

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