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@ZERICO2005 ZERICO2005 commented Jul 8, 2025

Wrote __dtof in assembly. Currently it raises no signals and is hard-coded to round-to-even.

  • FE_OVERFLOW and ERANGE could be raised if a finite input overflows to infinity, or if the result was rounded to infinity (such as (float)(FLT_MAX + 0.5ulp)).
  • FE_UNDERFLOW and ERANGE could be raised if a non-zero input becomes zero.
  • FE_INEXACT could be raised if the result was rounded.
Convert BC:UDE:UHL F64 to E:UHL F32
Rounding: round to nearest with ties to even
Behaviour:
  Underflow: Returns signed zero. No signals raised.
  Subnormal: No signals raised.
  Rounded to Infinity: No signals raised.
  Overflow: Returns signed infinity. No signals raised.
  Signaling NaN: Quiet bit preserved. No signals raised.
  Quiet NaN: Quiet bit preserved. No signals raised.
  NaN Payloads: Copies the most significant payload bits. The LSB of mantissa is set if payload bits were discarded/truncated out.

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ZERICO2005 commented Sep 20, 2025

I suppose raising signals and errno could be implemented later on if needed. And similar routines such as ftol and dtol don't raise any signals on overflow/inexact

@ZERICO2005 ZERICO2005 marked this pull request as ready for review September 20, 2025 23:36
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