Skip to content

Commit c81a5b8

Browse files
zRedShiftandreisfr
zRedShift
authored and
andreisfr
committed
[Xtensa] Add CLAMPS feature
1 parent 26ca9b6 commit c81a5b8

14 files changed

+87
-23
lines changed

‎llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -381,7 +381,7 @@ struct XtensaOperand : public MCParsedAsmOperand {
381381
return false;
382382
}
383383

384-
bool isseimm7_22() const { return isImm(7, 22); }
384+
bool isimm7_22() const { return isImm(7, 22); }
385385

386386
bool isSelect_2() const { return isImm(0, 1); }
387387

@@ -741,7 +741,7 @@ bool XtensaAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
741741
case Match_Invalidentry_imm12:
742742
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
743743
"expected immediate in range [0, 32760]");
744-
case Match_Invalidseimm7_22:
744+
case Match_Invalidimm7_22:
745745
return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
746746
"expected immediate in range [7, 22]");
747747
case Match_InvalidSelect_2:

‎llvm/lib/Target/Xtensa/Disassembler/XtensaDisassembler.cpp‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -576,9 +576,9 @@ static DecodeStatus decodeShimm1_31Operand(MCInst &Inst, uint64_t Imm,
576576
return MCDisassembler::Success;
577577
}
578578

579-
static DecodeStatus decodeSeimm7_22Operand(MCInst &Inst, uint64_t Imm,
580-
int64_t Address,
581-
const void *Decoder) {
579+
static DecodeStatus decodeImm7_22Operand(MCInst &Inst, uint64_t Imm,
580+
int64_t Address,
581+
const void *Decoder) {
582582
assert(isUInt<4>(Imm) && "Invalid immediate");
583583
Inst.addOperand(MCOperand::createImm(Imm + 7));
584584
return MCDisassembler::Success;

‎llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -438,8 +438,8 @@ void XtensaInstPrinter::printB4constu_AsmOperand(const MCInst *MI, int OpNum,
438438
printOperand(MI, OpNum, O);
439439
}
440440

441-
void XtensaInstPrinter::printSeimm7_22_AsmOperand(const MCInst *MI, int OpNum,
442-
raw_ostream &O) {
441+
void XtensaInstPrinter::printImm7_22_AsmOperand(const MCInst *MI, int OpNum,
442+
raw_ostream &O) {
443443
if (MI->getOperand(OpNum).isImm()) {
444444
int64_t Value = MI->getOperand(OpNum).getImm();
445445
assert((Value >= 7 && Value <= 22) &&

‎llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@ class XtensaInstPrinter : public MCInstPrinter {
6969
void printEntry_Imm12_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
7070
void printB4const_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
7171
void printB4constu_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
72-
void printSeimm7_22_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
72+
void printImm7_22_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
7373
void printSelect_2_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
7474
void printSelect_4_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
7575
void printSelect_8_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);

‎llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCCodeEmitter.cpp‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -139,9 +139,9 @@ class XtensaMCCodeEmitter : public MCCodeEmitter {
139139
SmallVectorImpl<MCFixup> &Fixups,
140140
const MCSubtargetInfo &STI) const;
141141

142-
uint32_t getSeimm7_22OpValue(const MCInst &MI, unsigned OpNo,
143-
SmallVectorImpl<MCFixup> &Fixups,
144-
const MCSubtargetInfo &STI) const;
142+
uint32_t getImm7_22OpValue(const MCInst &MI, unsigned OpNo,
143+
SmallVectorImpl<MCFixup> &Fixups,
144+
const MCSubtargetInfo &STI) const;
145145

146146
uint8_t getSelect_2OpValue(const MCInst &MI, unsigned OpNo,
147147
SmallVectorImpl<MCFixup> &Fixups,
@@ -628,9 +628,9 @@ XtensaMCCodeEmitter::getB4constuOpValue(const MCInst &MI, unsigned OpNo,
628628
}
629629

630630
uint32_t
631-
XtensaMCCodeEmitter::getSeimm7_22OpValue(const MCInst &MI, unsigned OpNo,
632-
SmallVectorImpl<MCFixup> &Fixups,
633-
const MCSubtargetInfo &STI) const {
631+
XtensaMCCodeEmitter::getImm7_22OpValue(const MCInst &MI, unsigned OpNo,
632+
SmallVectorImpl<MCFixup> &Fixups,
633+
const MCSubtargetInfo &STI) const {
634634
const MCOperand &MO = MI.getOperand(OpNo);
635635
uint32_t res = static_cast<uint32_t>(MO.getImm());
636636

‎llvm/lib/Target/Xtensa/Xtensa.td‎

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,11 @@ def FeatureSEXT : SubtargetFeature<"sext", "HasSEXT", "true",
4747
def HasSEXT : Predicate<"Subtarget->hasSEXT()">,
4848
AssemblerPredicate<(all_of FeatureSEXT)>;
4949

50+
def FeatureCLAMPS : SubtargetFeature<"clamps", "HasCLAMPS", "true",
51+
"Enable Xtensa CLAMPS option">;
52+
def HasCLAMPS : Predicate<"Subtarget->hasCLAMPS()">,
53+
AssemblerPredicate<(all_of FeatureCLAMPS)>;
54+
5055
def FeatureNSA : SubtargetFeature<"nsa", "HasNSA", "true",
5156
"Enable Xtensa NSA option">;
5257
def HasNSA : Predicate<"Subtarget->hasNSA()">,
@@ -185,21 +190,21 @@ def : Proc<"esp32", [FeatureDensity, FeatureSingleFloat, FeatureLoop, FeatureMAC
185190
FeatureNSA, FeatureMul16, FeatureMul32, FeatureMul32High, FeatureDFPAccel, FeatureS32C1I, FeatureTHREADPTR, FeatureDiv32,
186191
FeatureATOMCTL, FeatureMEMCTL, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor,
187192
FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR,
188-
FeatureMINMAX]>;
193+
FeatureMINMAX, FeatureCLAMPS]>;
189194

190195
def : Proc<"esp8266", [FeatureDensity, FeatureNSA, FeatureMul16, FeatureMul32, FeatureExtendedL32R, FeatureDebug, FeatureException,
191196
FeatureHighPriInterrupts, FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeatureRegionProtection, FeaturePRID]>;
192197

193198
def : Proc<"esp32s2", [FeatureDensity, FeatureWindowed, FeatureSEXT, FeatureNSA, FeatureMul16, FeatureMul32, FeatureMul32High, FeatureTHREADPTR,
194199
FeatureDiv32, FeatureMEMCTL, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor, FeatureInterrupt,
195200
FeatureRelocatableVector, FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR, FeatureMINMAX,
196-
FeatureESP32S2Ops]>;
201+
FeatureCLAMPS, FeatureESP32S2Ops]>;
197202

198203
def : Proc<"esp32s3", [FeatureDensity, FeatureSingleFloat, FeatureLoop, FeatureMAC16, FeatureWindowed, FeatureBoolean, FeatureSEXT,
199204
FeatureNSA, FeatureMul16, FeatureMul32, FeatureMul32High, FeatureDFPAccel, FeatureS32C1I, FeatureTHREADPTR, FeatureDiv32,
200205
FeatureATOMCTL, FeatureMEMCTL, FeatureDebug, FeatureException, FeatureHighPriInterrupts, FeatureCoprocessor,
201206
FeatureInterrupt, FeatureRelocatableVector, FeatureTimerInt, FeaturePRID, FeatureRegionProtection, FeatureMiscSR,
202-
FeatureMINMAX, FeatureESP32S3Ops]>;
207+
FeatureMINMAX, FeatureCLAMPS, FeatureESP32S3Ops]>;
203208

204209
//===----------------------------------------------------------------------===//
205210
// Register File Description

‎llvm/lib/Target/Xtensa/XtensaInstrInfo.td‎

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1334,13 +1334,24 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 0, Size =
13341334
// SEXT Instructions
13351335
//===----------------------------------------------------------------------===//
13361336

1337-
def SEXT : RRR_Inst<0x00, 0x03, 0x02, (outs AR:$r), (ins AR:$s, seimm7_22:$imm),
1337+
def SEXT : RRR_Inst<0x00, 0x03, 0x02, (outs AR:$r), (ins AR:$s, imm7_22:$imm),
13381338
"sext\t$r, $s, $imm", []>, Requires<[HasSEXT]> {
13391339
bits<4> imm;
13401340

13411341
let t = imm;
13421342
}
13431343

1344+
//===----------------------------------------------------------------------===//
1345+
// CLAMPS Instructions
1346+
//===----------------------------------------------------------------------===//
1347+
1348+
def CLAMPS : RRR_Inst<0x00, 0x03, 0x03, (outs AR:$r), (ins AR:$s, imm7_22:$imm),
1349+
"clamps\t$r, $s, $imm", []>, Requires<[HasSEXT]> {
1350+
bits<4> imm;
1351+
1352+
let t = imm;
1353+
}
1354+
13441355
//===----------------------------------------------------------------------===//
13451356
// NSA Instructions
13461357
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/Xtensa/XtensaOperands.td‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -168,11 +168,11 @@ def b4constu: Immediate<i32,
168168
let DecoderMethod = "decodeB4constuOperand";
169169
}
170170

171-
// seimm7_22 predicate - Immediate in the range [7,22] for sign extend
172-
def Seimm7_22_AsmOperand: ImmAsmOperand<"seimm7_22">;
173-
def seimm7_22: Immediate<i32, [{ return Imm >= 7 && Imm <= 22; }], "Seimm7_22_AsmOperand"> {
174-
let EncoderMethod = "getSeimm7_22OpValue";
175-
let DecoderMethod = "decodeSeimm7_22Operand";
171+
// imm7_22 predicate - Immediate in the range [7,22] for sign extend and clamps
172+
def Imm7_22_AsmOperand: ImmAsmOperand<"imm7_22">;
173+
def imm7_22: Immediate<i32, [{ return Imm >= 7 && Imm <= 22; }], "Imm7_22_AsmOperand"> {
174+
let EncoderMethod = "getImm7_22OpValue";
175+
let DecoderMethod = "decodeImm7_22Operand";
176176
}
177177

178178
// select_256 predicate - Immediate in the range [0,255]

‎llvm/lib/Target/Xtensa/XtensaSubtarget.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,7 @@ XtensaSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) {
5151
HasBoolean = false;
5252
HasLoop = false;
5353
HasSEXT = false;
54+
HasCLAMPS = false;
5455
HasNSA = false;
5556
HasMINMAX = false;
5657
HasMul16 = false;

‎llvm/lib/Target/Xtensa/XtensaSubtarget.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -56,6 +56,9 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo {
5656
// Enable Xtensa Sign Extend option
5757
bool HasSEXT;
5858

59+
// Enable Xtensa CLAMPS option
60+
bool HasCLAMPS;
61+
5962
// Enable Xtensa NSA option
6063
bool HasNSA;
6164

@@ -160,6 +163,8 @@ class XtensaSubtarget : public XtensaGenSubtargetInfo {
160163

161164
bool hasSEXT() const { return HasSEXT; }
162165

166+
bool hasCLAMPS() const { return HasCLAMPS; }
167+
163168
bool hasNSA() const { return HasNSA; }
164169

165170
bool hasMINMAX() const { return HasMINMAX; }

0 commit comments

Comments
 (0)