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[ESP32P4] Fix imm ranges.
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9 files changed

+82
-13
lines changed

9 files changed

+82
-13
lines changed

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -516,6 +516,11 @@ struct RISCVOperand final : public MCParsedAsmOperand {
516516
((cast<MCConstantExpr>(getImm())->getValue() & 0xf) == 0);
517517
}
518518

519+
bool isOffset_256_2() const {
520+
return isImm(-256, 254) &&
521+
((cast<MCConstantExpr>(getImm())->getValue() & 0x1) == 0);
522+
}
523+
519524
bool isOffset_256_4() const {
520525
return isImm(-512, 508) &&
521526
((cast<MCConstantExpr>(getImm())->getValue() & 0x3) == 0);

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp‎

Lines changed: 26 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -511,6 +511,14 @@ static DecodeStatus decodeOffset_256_16Operand(MCInst &Inst, int64_t Imm,
511511
int64_t Address,
512512
const void *Decoder);
513513

514+
static DecodeStatus decodeImm8Operand(MCInst &Inst, uint64_t Imm,
515+
int64_t Address,
516+
const void *Decoder);
517+
518+
static DecodeStatus decodeOffset_256_2Operand(MCInst &Inst, int64_t Imm,
519+
int64_t Address,
520+
const void *Decoder);
521+
514522
static DecodeStatus decodeOffset_256_4Operand(MCInst &Inst, int64_t Imm,
515523
int64_t Address,
516524
const void *Decoder);
@@ -701,11 +709,27 @@ static DecodeStatus decodeOffset_256_16Operand(MCInst &Inst, int64_t Imm,
701709
return MCDisassembler::Success;
702710
}
703711

704-
static DecodeStatus decodeOffset_256_4Operand(MCInst &Inst, int64_t Imm,
712+
static DecodeStatus decodeImm8Operand(MCInst &Inst, uint64_t Imm,
713+
int64_t Address, const void *Decoder) {
714+
assert(isUInt<8>(Imm) && "Invalid immediate");
715+
Inst.addOperand(MCOperand::createImm(SignExtend64<8>(Imm)));
716+
return MCDisassembler::Success;
717+
}
718+
719+
static DecodeStatus decodeOffset_256_2Operand(MCInst &Inst, int64_t Imm,
705720
int64_t Address,
706721
const void *Decoder) {
707722
assert(isInt<16>(Imm) && "Invalid immediate");
708-
auto ImmSigned = SignExtend64<4>(Imm);
723+
auto ImmSigned = SignExtend64<8>(Imm);
724+
Inst.addOperand(MCOperand::createImm(ImmSigned * 2));
725+
return MCDisassembler::Success;
726+
}
727+
728+
static DecodeStatus decodeOffset_256_4Operand(MCInst &Inst, int64_t Imm,
729+
int64_t Address,
730+
const void *Decoder) {
731+
assert(isInt<32>(Imm) && "Invalid immediate");
732+
auto ImmSigned = SignExtend64<8>(Imm);
709733
Inst.addOperand(MCOperand::createImm(ImmSigned * 4));
710734
return MCDisassembler::Success;
711735
}

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -415,6 +415,19 @@ void RISCVInstPrinter::printOffset_256_16_AsmOperand(const MCInst *MI,
415415
}
416416
}
417417

418+
void RISCVInstPrinter::printOffset_256_2_AsmOperand(const MCInst *MI, int OpNum,
419+
const MCSubtargetInfo &STI,
420+
raw_ostream &O) {
421+
if (MI->getOperand(OpNum).isImm()) {
422+
int64_t Value = MI->getOperand(OpNum).getImm();
423+
assert((Value >= -256 && Value <= 254 && (Value & 0x1) == 0) &&
424+
"Invalid argument, value must be in range [-256,254], first 1 bits "
425+
"should be zero");
426+
O << Value;
427+
} else
428+
printOperand(MI, OpNum, STI, O);
429+
}
430+
418431
void RISCVInstPrinter::printOffset_256_4_AsmOperand(const MCInst *MI, int OpNum,
419432
const MCSubtargetInfo &STI,
420433
raw_ostream &O) {

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -91,6 +91,8 @@ class RISCVInstPrinter : public MCInstPrinter {
9191
void printOffset_256_16_AsmOperand(const MCInst *MI, int OpNum,
9292
const MCSubtargetInfo &STI,
9393
raw_ostream &O);
94+
void printOffset_256_2_AsmOperand(const MCInst *MI, int OpNum,
95+
const MCSubtargetInfo &STI, raw_ostream &O);
9496
void printOffset_256_4_AsmOperand(const MCInst *MI, int OpNum,
9597
const MCSubtargetInfo &STI, raw_ostream &O);
9698
};

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,10 @@ class RISCVMCCodeEmitter : public MCCodeEmitter {
135135
int16_t getOffset_256_8OpValue(const MCInst &MI, unsigned OpNo,
136136
SmallVectorImpl<MCFixup> &Fixups,
137137
const MCSubtargetInfo &STI) const;
138+
139+
int16_t getOffset_256_2OpValue(const MCInst &MI, unsigned OpNo,
140+
SmallVectorImpl<MCFixup> &Fixups,
141+
const MCSubtargetInfo &STI) const;
138142

139143
int16_t getOffset_256_4OpValue(const MCInst &MI, unsigned OpNo,
140144
SmallVectorImpl<MCFixup> &Fixups,
@@ -729,6 +733,19 @@ RISCVMCCodeEmitter::getOffset_256_16OpValue(const MCInst &MI, unsigned OpNo,
729733
return Res / 16;
730734
}
731735

736+
int16_t
737+
RISCVMCCodeEmitter::getOffset_256_2OpValue(const MCInst &MI, unsigned OpNo,
738+
SmallVectorImpl<MCFixup> &Fixups,
739+
const MCSubtargetInfo &STI) const {
740+
const MCOperand &MO = MI.getOperand(OpNo);
741+
int16_t Res = static_cast<int16_t>(MO.getImm());
742+
743+
assert(((Res >= -256) && (Res <= 254) && ((Res & 0x1) == 0)) &&
744+
"Unexpected operand value!");
745+
746+
return Res / 2;
747+
}
748+
732749
int16_t
733750
RISCVMCCodeEmitter::getOffset_256_4OpValue(const MCInst &MI, unsigned OpNo,
734751
SmallVectorImpl<MCFixup> &Fixups,

‎llvm/lib/Target/RISCV/RISCVESP32P4Operands.td‎

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,15 @@ def offset_256_16: Immediate<i32, [{ return (Imm >= -2048 && Imm <= 2032) && ((I
5353
let DecoderMethod = "decodeOffset_256_16Operand";
5454
}
5555

56-
// offset_256_4 predicate - 4-bit signed immediate in the range [-512,508] with an interval
56+
// offset_256_2 predicate - 8-bit signed immediate in the range [-256,254] with an interval
57+
// of 2.
58+
def Offset_256_2_AsmOperand: P4ImmAsmOperand<"Offset_256_2">;
59+
def offset_256_2: Immediate<i32, [{ return (Imm >= -256 && Imm <= 254) && ((Imm & 0x1) == 0); }], "Offset_256_2_AsmOperand"> {
60+
let EncoderMethod = "getOffset_256_2OpValue";
61+
let DecoderMethod = "decodeOffset_256_2Operand";
62+
}
63+
64+
// offset_256_4 predicate - 8-bit signed immediate in the range [-512,508] with an interval
5765
// of 4.
5866
def Offset_256_4_AsmOperand: P4ImmAsmOperand<"Offset_256_4">;
5967
def offset_256_4: Immediate<i32, [{ return (Imm >= -512 && Imm <= 508) && ((Imm & 0x3) == 0); }], "Offset_256_4_AsmOperand"> {

‎llvm/lib/Target/RISCV/RISCVInstrInfoESP32P4.td‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -12527,7 +12527,7 @@ def ESP_LDQA_U8_128_XP_P : PseudoESP32P4<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs2,
1252712527
"!esp_ldqa_u8_128_xp_p $rs1, $rs2",
1252812528
[(set GPRPIE:$rs1r, (int_riscv_esp_ldqa_u8_128_xp GPRPIE:$rs2, GPRPIE:$rs1))]>;
1252912529

12530-
def ESP_VLDBC_16_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_4:$off2564),
12530+
def ESP_VLDBC_16_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_2:$off2564),
1253112531
"esp.vldbc.16.ip\t $qu, $rs1, $off2564", []>
1253212532
{
1253312533
bits<5> rs1;
@@ -12566,7 +12566,7 @@ def ESP_VLDBC_16_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs1,
1256612566
}
1256712567

1256812568
let usesCustomInserter = 1, Constraints = "$rs1r = $rs1" in
12569-
def ESP_VLDBC_16_IP_P : PseudoESP32P4<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_4:$off2564, imm8:$qu),
12569+
def ESP_VLDBC_16_IP_P : PseudoESP32P4<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_2:$off2564, imm8:$qu),
1257012570
"!esp_vldbc_16_ip_p $qu, $rs1, $off2564",
1257112571
[(set GPRPIE:$rs1r, (int_riscv_esp_vldbc_16_ip GPRPIE:$rs1, timm:$off2564, timm:$qu))]>;
1257212572

@@ -12705,7 +12705,7 @@ def ESP_VLDBC_32_XP_P : PseudoESP32P4<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs2, GPR
1270512705
"!esp_vldbc_32_xp_p $qu, $rs1, $rs2",
1270612706
[(set GPRPIE:$rs1r, (int_riscv_esp_vldbc_32_xp GPRPIE:$rs2, GPRPIE:$rs1, timm:$qu))]>;
1270712707

12708-
def ESP_VLDBC_8_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_4:$off2564),
12708+
def ESP_VLDBC_8_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs1, imm8:$off2564),
1270912709
"esp.vldbc.8.ip\t $qu, $rs1, $off2564", []>
1271012710
{
1271112711
bits<5> rs1;
@@ -12744,7 +12744,7 @@ def ESP_VLDBC_8_IP: Esp32P4Inst<(outs QR:$qu, GPRPIE:$rs1r), (ins GPRPIE:$rs1, o
1274412744
}
1274512745

1274612746
let usesCustomInserter = 1, Constraints = "$rs1r = $rs1" in
12747-
def ESP_VLDBC_8_IP_P : PseudoESP32P4<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs1, offset_256_4:$off2564, imm8:$qu),
12747+
def ESP_VLDBC_8_IP_P : PseudoESP32P4<(outs GPRPIE:$rs1r), (ins GPRPIE:$rs1, imm8:$off2564, imm8:$qu),
1274812748
"!esp_vldbc_8_ip_p $qu, $rs1, $off2564",
1274912749
[(set GPRPIE:$rs1r, (int_riscv_esp_vldbc_8_ip GPRPIE:$rs1, timm:$off2564, timm:$qu))]>;
1275012750

‎llvm/test/CodeGen/RISCV/esp32p4.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -470,7 +470,7 @@ define void @test(){
470470
; CHECK-NEXT: li a1, 6
471471
; CHECK-NEXT: esp.vldbc.32.xp q3, a1, a5
472472
; CHECK-NEXT: li a1, 6
473-
; CHECK-NEXT: esp.vldbc.8.ip q4, a1, -492
473+
; CHECK-NEXT: esp.vldbc.8.ip q4, a1, -112
474474
; CHECK-NEXT: li a1, 9
475475
; CHECK-NEXT: esp.vldbc.8.xp q6, a1, a5
476476
; CHECK-NEXT: li a1, 10
@@ -867,7 +867,7 @@ define void @test(){
867867
%142 = tail call i32 @llvm.riscv.esp.vldbc.16.xp(i32 3, i32 2, i32 2)
868868
%143 = tail call i32 @llvm.riscv.esp.vldbc.32.ip(i32 8, i32 396, i32 5)
869869
%144 = tail call i32 @llvm.riscv.esp.vldbc.32.xp(i32 14, i32 6, i32 3)
870-
%145 = tail call i32 @llvm.riscv.esp.vldbc.8.ip(i32 6, i32 -492, i32 4)
870+
%145 = tail call i32 @llvm.riscv.esp.vldbc.8.ip(i32 6, i32 -112, i32 4)
871871
%146 = tail call i32 @llvm.riscv.esp.vldbc.8.xp(i32 14, i32 9, i32 6)
872872
%147 = tail call i32 @llvm.riscv.esp.vldext.s16.ip(i32 10, i32 32, i32 6, i32 2)
873873
%148 = tail call i32 @llvm.riscv.esp.vldext.s16.xp(i32 11, i32 0, i32 2, i32 6)

‎llvm/test/MC/RISCV/esp32p4-valid.s‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -570,16 +570,16 @@ esp.ldqa.u8.128.ip a2, 1200
570570
# CHECK: esp.ldqa.u8.128.ip a2, 1200 # encoding: [0xbb,0x56,0x42,0x20]
571571
esp.ldqa.u8.128.xp a2, a5
572572
# CHECK: esp.ldqa.u8.128.xp a2, a5 # encoding: [0x5b,0x50,0x72,0x13]
573-
esp.vldbc.16.ip q4, a3, 408
574-
# CHECK: esp.vldbc.16.ip q4, a3, 408 # encoding: [0x3b,0xb0,0x32,0xb6]
573+
esp.vldbc.16.ip q4, a3, 200
574+
# CHECK: esp.vldbc.16.ip q4, a3, 200 # encoding: [0x3b,0xb0,0x22,0xb6]
575575
esp.vldbc.16.xp q5, a2, a1
576576
# CHECK: esp.vldbc.16.xp q5, a2, a1 # encoding: [0x5f,0x54,0x32,0x96]
577577
esp.vldbc.32.ip q6, a2, -176
578578
# CHECK: esp.vldbc.32.ip q6, a2, -176 # encoding: [0x3b,0x38,0xa2,0xce]
579579
esp.vldbc.32.xp q0, a1, a2
580580
# CHECK: esp.vldbc.32.xp q0, a1, a2 # encoding: [0x5f,0xc0,0x41,0x8e]
581-
esp.vldbc.8.ip q6, a0, 200
582-
# CHECK: esp.vldbc.8.ip q6, a0, 200 # encoding: [0x3b,0x38,0x91,0x16]
581+
esp.vldbc.8.ip q6, a0, 112
582+
# CHECK: esp.vldbc.8.ip q6, a0, 112 # encoding: [0x3b,0x38,0x81,0x36]
583583
esp.vldbc.8.xp q5, a4, a2
584584
# CHECK: esp.vldbc.8.xp q5, a4, a2 # encoding: [0x5f,0x54,0x43,0x86]
585585
esp.vldext.s16.ip q4, q1, a3, -112

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