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Update Versal JESD204 PHY to the new Versal Subsystem
Signed-off-by: Bogdan Luncan <[email protected]>
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‎library/xilinx/scripts/versal_xcvr_subsystem.tcl

Lines changed: 333 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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###############################################################################
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## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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source ../../../projects/scripts/adi_board.tcl
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# Parameter description:
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# ip_name : The name of the created ip
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# jesd_mode : Used physical layer encoder mode
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# rx_no_lanes : Number of RX lanes
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# tx_no_lanes : Number of TX lanes
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# ref_clock : Frequency of reference clock in MHz used in 64B66B mode (LANE_RATE/66) or 8B10B mode (LANE_RATE/40)
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# rx_lane_rate : Line rate of the Rx link ( e.g. MxFE to FPGA ) in GHz
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# tx_lane_rate : Line rate of the Tx link ( e.g. FPGA to MxFE ) in GHz
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# transceiver : Type of transceiver to use (GTY or GTYP)
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# direction : Direction of the transceivers
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# RXTX : Duplex mode
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# RX : Rx link only
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# TX : Tx link only
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proc create_xcvr_subsystem {
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{ip_name xcvr}
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{jesd_mode 64B66B}
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{rx_no_lanes 4}
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{tx_no_lanes 4}
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{rx_lane_rate 24.75}
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{tx_lane_rate 24.75}
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{ref_clock 375}
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{transceiver GTY}
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{direction RX}
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} {
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set clk_divider [expr {$jesd_mode == "64B66B" ? 66 : 40}]
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set datapath_width [expr {$jesd_mode == "64B66B" ? 64 : 32}]
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set internal_datapath_width [expr {$jesd_mode == "64B66B" ? 64 : 40}]
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set data_encoding [expr {$jesd_mode == "64B66B" ? "64B66B_ASYNC" : "8B10B"}]
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set comma_mask [expr {$jesd_mode == "64B66B" ? "0000000000" : "1111111111"}]
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set comma_p_enable [expr {$jesd_mode == "64B66B" ? false : false}]
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set comma_m_enable [expr {$jesd_mode == "64B66B" ? false : false}]
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set rx_progdiv_clock [format %.3f [expr $rx_lane_rate * 1000.0 / ${clk_divider}]]
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set tx_progdiv_clock [format %.3f [expr $tx_lane_rate * 1000.0 / ${clk_divider}]]
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if {$direction == "RXTX"} {
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set no_lanes [expr max($rx_no_lanes, $tx_no_lanes)]
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} elseif {$direction == "RX"} {
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set no_lanes $rx_no_lanes
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} else {
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set no_lanes $tx_no_lanes
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}
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set num_quads [expr int(ceil(1.0 * $no_lanes / 4))]
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ad_ip_instance gtwiz_versal ${ip_name}
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set xcvr_param [dict create]
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# RX parameters
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dict set xcvr_param RX_LINE_RATE ${rx_lane_rate}
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dict set xcvr_param RX_DATA_DECODING ${data_encoding}
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dict set xcvr_param RX_REFCLK_FREQUENCY ${ref_clock}
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dict set xcvr_param RX_USER_DATA_WIDTH ${datapath_width}
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dict set xcvr_param RX_INT_DATA_WIDTH ${internal_datapath_width}
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dict set xcvr_param RX_OUTCLK_SOURCE {RXPROGDIVCLK}
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dict set xcvr_param RXRECCLK_FREQ_VAL ${rx_progdiv_clock}
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dict set xcvr_param RXPROGDIV_FREQ_VAL ${rx_progdiv_clock}
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if {$jesd_mode == "8B10B"} {
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dict set xcvr_param RX_COMMA_P_ENABLE ${comma_p_enable}
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dict set xcvr_param RX_COMMA_M_ENABLE ${comma_m_enable}
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dict set xcvr_param RX_COMMA_SHOW_REALIGN_ENABLE {false}
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dict set xcvr_param RX_SLIDE_MODE {PCS}
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}
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# Tx parameters
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dict set xcvr_param TX_LINE_RATE ${tx_lane_rate}
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dict set xcvr_param TX_DATA_ENCODING ${data_encoding}
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dict set xcvr_param TX_REFCLK_FREQUENCY ${ref_clock}
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dict set xcvr_param TX_USER_DATA_WIDTH ${datapath_width}
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dict set xcvr_param TX_INT_DATA_WIDTH ${internal_datapath_width}
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dict set xcvr_param TXPROGDIV_FREQ_VAL ${tx_progdiv_clock}
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dict set xcvr_param TX_OUTCLK_SOURCE {TXPROGDIVCLK}
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set phy_params [dict create]
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dict set phy_params CONFIG.ENABLE_REG_INTERFACE {true}
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dict set phy_params CONFIG.REG_CONF_INTF {AXI_LITE}
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dict set phy_params CONFIG.NO_OF_QUADS ${num_quads}
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dict set phy_params CONFIG.NO_OF_INTERFACE {1}
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dict set phy_params CONFIG.LOCATE_BUFG {CORE}
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dict set phy_params CONFIG.INTF0_PRESET ${transceiver}-JESD204_${jesd_mode}
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dict set phy_params CONFIG.INTF0_GT_SETTINGS(LR0_SETTINGS) ${xcvr_param}
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if {$direction != "RXTX"} {
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dict set phy_params CONFIG.INTF0_GT_DIRECTION SIMPLEX_${direction}
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dict set phy_params CONFIG.INTF0_NO_OF_LANES ${no_lanes}
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} else {
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# When RXTX is selected, create two interfaces
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# Interface 0 for RX
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# Interface 1 for TX
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# This is mandatory if we want to have different number of lanes for RX and TX
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dict set phy_params CONFIG.NO_OF_INTERFACE {2}
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dict set phy_params CONFIG.INTF0_GT_DIRECTION {SIMPLEX_RX}
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dict set phy_params CONFIG.INTF1_GT_DIRECTION {SIMPLEX_TX}
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dict set phy_params CONFIG.INTF0_NO_OF_LANES $rx_no_lanes
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dict set phy_params CONFIG.INTF1_NO_OF_LANES $tx_no_lanes
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dict set phy_params CONFIG.INTF1_PRESET ${transceiver}-JESD204_${jesd_mode}
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dict set phy_params CONFIG.INTF1_GT_SETTINGS(LR0_SETTINGS) ${xcvr_param}
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}
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if {$direction != "RXTX"} {
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# Simplex RX or Simplex TX
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# One single interface (Interface 0)
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dict set phy_params "CONFIG.QUAD0_${direction}0_OUTCLK_EN" {true}
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dict set phy_params "CONFIG.QUAD0_PROT0_${direction}MSTCLK" ${direction}0
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for {set i 0} {$i < [expr 4 * $num_quads]} {incr i} {
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set quad_idx [expr $i / 4]
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set lane_idx [expr $i % 4]
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dict set phy_params "CONFIG.QUAD${quad_idx}_PROT0_${direction}${lane_idx}_EN" [expr $i < $no_lanes]
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}
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for {set i 0} {$i < $num_quads} {incr i} {
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dict set phy_params "CONFIG.QUAD${i}_PROT0_LANES" [expr min(4, max(0, $no_lanes - 4 * $i))]
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}
119+
} else {
120+
# Interface 0 = RX
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# Interface 1 = TX
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dict set phy_params "CONFIG.QUAD0_RX0_OUTCLK_EN" {true}
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dict set phy_params "CONFIG.QUAD0_TX0_OUTCLK_EN" {true}
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dict set phy_params "CONFIG.QUAD0_PROT0_RXMSTCLK" {RX0}
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# Map RX lanes
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for {set i 0} {$i < $num_quads} {incr i} {
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set lanes [expr min(4, max(0, $rx_no_lanes - 4 * $i))]
129+
if {$lanes != 0} {
130+
dict set phy_params "CONFIG.QUAD${i}_PROT0_LANES" ${lanes}
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dict set phy_params "CONFIG.QUAD${i}_NO_PROT" {1}
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}
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}
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for {set i 0} {$i < [expr 4 * $num_quads]} {incr i} {
135+
set quad_idx [expr $i / 4]
136+
set lane_idx [expr $i % 4]
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dict set phy_params "CONFIG.QUAD${quad_idx}_PROT0_RX${lane_idx}_EN" [expr $i < $rx_no_lanes]
138+
}
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# Map TX lanes
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dict set phy_params "CONFIG.QUAD0_PROT1_TXMSTCLK" {TX0}
142+
for {set i 0} {$i < $num_quads} {incr i} {
143+
set lanes [expr min(4, max(0, $tx_no_lanes - 4 * $i))]
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if {$lanes != 0} {
145+
if {[dict exists $phy_params "CONFIG.QUAD${i}_PROT0_LANES"]} {
146+
# Both RX and TX lanes in the same quad
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dict set phy_params "CONFIG.QUAD${i}_NO_PROT" {2}
148+
dict set phy_params "CONFIG.QUAD${i}_PROT1_LANES" ${lanes}
149+
} else {
150+
# Only TX lanes in this quad
151+
dict set phy_params "CONFIG.QUAD${i}_NO_PROT" {1}
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dict set phy_params "CONFIG.QUAD${i}_PROT0" {INTF1}
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dict set phy_params "CONFIG.QUAD${i}_PROT0_LANES" ${lanes}
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}
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}
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}
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for {set i 0} {$i < [expr 4 * $num_quads]} {incr i} {
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set quad_idx [expr $i / 4]
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set lane_idx [expr $i % 4]
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set prot_idx [expr {[dict get $phy_params "CONFIG.QUAD${quad_idx}_NO_PROT"] - 1}]
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dict set phy_params "CONFIG.QUAD${quad_idx}_PROT${prot_idx}_TX${lane_idx}_EN" [expr $i < $tx_no_lanes]
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}
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}
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# dict for {k v} $phy_params {puts "$k : $v"}
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set_property -dict $phy_params [get_bd_cells ${ip_name}]
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}
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# Parameter description:
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# ip_name : The name of the created ip
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# jesd_mode : Used physical layer encoder mode
172+
# rx_no_lanes : Number of RX lanes
173+
# tx_no_lanes : Number of TX lanes
174+
# ref_clock : Frequency of reference clock in MHz used in 64B66B mode (LANE_RATE/66) or 8B10B mode (LANE_RATE/40)
175+
# rx_lane_rate : Line rate of the Rx link ( e.g. MxFE to FPGA ) in GHz
176+
# tx_lane_rate : Line rate of the Tx link ( e.g. FPGA to MxFE ) in GHz
177+
# transceiver : Type of transceiver to use (GTY or GTYP)
178+
# intf_cfg : Direction of the transceivers
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# RXTX : Duplex mode
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# RX : Rx link only
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# TX : Tx link only
182+
proc create_versal_jesd_xcvr_subsystem {
183+
{ip_name versal_phy}
184+
{jesd_mode 64B66B}
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{rx_no_lanes 4}
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{tx_no_lanes 4}
187+
{rx_lane_rate 24.75}
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{tx_lane_rate 24.75}
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{ref_clock 375}
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{transceiver GTY}
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{intf_cfg RXTX}
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} {
193+
set rx_quads [expr int(ceil(1.0 * $rx_no_lanes / 4))]
194+
set tx_quads [expr int(ceil(1.0 * $tx_no_lanes / 4))]
195+
set num_quads [expr max($rx_quads, $tx_quads)]
196+
set link_mode [expr {$jesd_mode == "64B66B" ? 2 : 1}]
197+
198+
if {$intf_cfg == "RXTX"} {
199+
set rx_intf 0
200+
set tx_intf 1
201+
} else {
202+
set rx_intf 0
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set tx_intf 0
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}
205+
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create_bd_cell -type hier ${ip_name}
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# Common interface
209+
create_bd_pin -dir I ${ip_name}/GT_REFCLK -type clk
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create_bd_pin -dir I ${ip_name}/s_axi_clk
211+
create_bd_pin -dir I ${ip_name}/s_axi_resetn
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if {$intf_cfg != "TX"} {
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create_bd_pin -dir O ${ip_name}/rxusrclk_out -type clk
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create_bd_pin -dir I ${ip_name}/en_char_align
215+
}
216+
if {$intf_cfg != "RX"} {
217+
create_bd_pin -dir O ${ip_name}/txusrclk_out -type clk
218+
}
219+
220+
create_xcvr_subsystem ${ip_name}/xcvr $jesd_mode $rx_no_lanes $tx_no_lanes $rx_lane_rate $tx_lane_rate $ref_clock $transceiver $intf_cfg
221+
222+
# Common xcvr connection
223+
for {set j 0} {$j < $num_quads} {incr j} {
224+
ad_connect ${ip_name}/GT_REFCLK ${ip_name}/xcvr/QUAD${j}_GTREFCLK0
225+
}
226+
227+
if {$intf_cfg != "TX"} {
228+
ad_ip_instance bufg_gt ${ip_name}/bufg_gt_rx
229+
ad_connect ${ip_name}/xcvr/INTF${rx_intf}_rx_clr_out ${ip_name}/bufg_gt_rx/gt_bufgtclr
230+
ad_connect ${ip_name}/xcvr/QUAD0_RX0_outclk ${ip_name}/bufg_gt_rx/outclk
231+
ad_connect ${ip_name}/bufg_gt_rx/usrclk ${ip_name}/rxusrclk_out
232+
233+
for {set j 0} {$j < $rx_quads} {incr j} {
234+
create_bd_pin -dir I -from 3 -to 0 ${ip_name}/rx_${j}_p
235+
create_bd_pin -dir I -from 3 -to 0 ${ip_name}/rx_${j}_n
236+
ad_connect ${ip_name}/xcvr/QUAD${j}_rxp ${ip_name}/rx_${j}_p
237+
ad_connect ${ip_name}/xcvr/QUAD${j}_rxn ${ip_name}/rx_${j}_n
238+
}
239+
240+
for {set j 0} {$j < $rx_no_lanes} {incr j} {
241+
ad_ip_instance jesd204_versal_gt_adapter_rx ${ip_name}/rx_adapt_${j} [list \
242+
LINK_MODE $link_mode \
243+
]
244+
ad_connect ${ip_name}/rx_adapt_${j}/RX_GT_IP_Interface ${ip_name}/xcvr/INTF${rx_intf}_RX${j}_GT_IP_Interface
245+
246+
create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 ${ip_name}/rx${j}
247+
ad_connect ${ip_name}/rx${j} ${ip_name}/rx_adapt_${j}/RX
248+
ad_connect ${ip_name}/rx_adapt_${j}/usr_clk ${ip_name}/xcvr/INTF${rx_intf}_rx_usrclk
249+
ad_connect ${ip_name}/rx_adapt_${j}/en_char_align ${ip_name}/en_char_align
250+
}
251+
}
252+
253+
if {$intf_cfg != "RX"} {
254+
ad_ip_instance bufg_gt ${ip_name}/bufg_gt_tx
255+
ad_connect ${ip_name}/xcvr/INTF${tx_intf}_tx_clr_out ${ip_name}/bufg_gt_tx/gt_bufgtclr
256+
ad_connect ${ip_name}/xcvr/QUAD0_TX0_outclk ${ip_name}/bufg_gt_tx/outclk
257+
ad_connect ${ip_name}/bufg_gt_tx/usrclk ${ip_name}/txusrclk_out
258+
259+
for {set j 0} {$j < $tx_quads} {incr j} {
260+
create_bd_pin -dir O -from 3 -to 0 ${ip_name}/tx_${j}_p
261+
create_bd_pin -dir O -from 3 -to 0 ${ip_name}/tx_${j}_n
262+
ad_connect ${ip_name}/xcvr/QUAD${j}_txp ${ip_name}/tx_${j}_p
263+
ad_connect ${ip_name}/xcvr/QUAD${j}_txn ${ip_name}/tx_${j}_n
264+
}
265+
266+
for {set j 0} {$j < $tx_no_lanes} {incr j} {
267+
ad_ip_instance jesd204_versal_gt_adapter_tx ${ip_name}/tx_adapt_${j} [list \
268+
LINK_MODE $link_mode \
269+
]
270+
ad_connect ${ip_name}/tx_adapt_${j}/TX_GT_IP_Interface ${ip_name}/xcvr/INTF${tx_intf}_TX${j}_GT_IP_Interface
271+
272+
create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 ${ip_name}/tx${j}
273+
ad_connect ${ip_name}/tx${j} ${ip_name}/tx_adapt_${j}/TX
274+
ad_connect ${ip_name}/tx_adapt_${j}/usr_clk ${ip_name}/xcvr/INTF${tx_intf}_tx_usrclk
275+
}
276+
}
277+
278+
# Reset signals
279+
create_bd_pin -dir I ${ip_name}/gtreset_in
280+
create_bd_pin -dir O ${ip_name}/gtpowergood
281+
if {$intf_cfg != "TX"} {
282+
create_bd_pin -dir I ${ip_name}/gtreset_rx_pll_and_datapath
283+
create_bd_pin -dir I ${ip_name}/gtreset_rx_datapath
284+
create_bd_pin -dir O ${ip_name}/rx_resetdone
285+
}
286+
if {$intf_cfg != "RX"} {
287+
create_bd_pin -dir I ${ip_name}/gtreset_tx_pll_and_datapath
288+
create_bd_pin -dir I ${ip_name}/gtreset_tx_datapath
289+
create_bd_pin -dir O ${ip_name}/tx_resetdone
290+
}
291+
292+
create_bd_cell -type module -reference sync_bits ${ip_name}/gtreset_sync
293+
ad_connect ${ip_name}/s_axi_clk ${ip_name}/gtreset_sync/out_clk
294+
ad_connect ${ip_name}/s_axi_resetn ${ip_name}/gtreset_sync/out_resetn
295+
ad_connect ${ip_name}/gtreset_in ${ip_name}/gtreset_sync/in_bits
296+
297+
298+
ad_connect ${ip_name}/gtreset_sync/out_bits ${ip_name}/xcvr/INTF${rx_intf}_rst_all_in
299+
if {$rx_intf != $tx_intf} {
300+
ad_connect ${ip_name}/gtreset_sync/out_bits ${ip_name}/xcvr/INTF${tx_intf}_rst_all_in
301+
}
302+
303+
foreach port {pll_and_datapath datapath} {
304+
foreach rx_tx {rx tx} {
305+
if {($rx_tx == "rx" && $intf_cfg == "TX") || ($rx_tx == "tx" && $intf_cfg == "RX")} {
306+
continue
307+
}
308+
set intf [expr {$rx_tx == "rx" ? $rx_intf : $tx_intf}]
309+
create_bd_cell -type module -reference sync_bits ${ip_name}/gtreset_${rx_tx}_${port}_sync
310+
ad_connect ${ip_name}/s_axi_clk ${ip_name}/gtreset_${rx_tx}_${port}_sync/out_clk
311+
ad_connect ${ip_name}/s_axi_resetn ${ip_name}/gtreset_${rx_tx}_${port}_sync/out_resetn
312+
ad_connect ${ip_name}/gtreset_${rx_tx}_${port} ${ip_name}/gtreset_${rx_tx}_${port}_sync/in_bits
313+
ad_connect ${ip_name}/gtreset_${rx_tx}_${port}_sync/out_bits ${ip_name}/xcvr/INTF${intf}_rst_${rx_tx}_${port}_in
314+
}
315+
}
316+
317+
ad_connect ${ip_name}/xcvr/gtpowergood ${ip_name}/gtpowergood
318+
if {$intf_cfg != "TX"} {
319+
ad_connect ${ip_name}/xcvr/INTF${rx_intf}_rst_rx_done_out ${ip_name}/rx_resetdone
320+
}
321+
if {$intf_cfg != "RX"} {
322+
ad_connect ${ip_name}/xcvr/INTF${tx_intf}_rst_tx_done_out ${ip_name}/tx_resetdone
323+
}
324+
325+
# AXI interface
326+
ad_connect ${ip_name}/s_axi_clk ${ip_name}/xcvr/gtwiz_freerun_clk
327+
for {set j 0} {$j < $num_quads} {incr j} {
328+
ad_connect ${ip_name}/s_axi_resetn ${ip_name}/xcvr/QUAD${j}_s_axi_lite_resetn
329+
330+
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 ${ip_name}/s_axi_${j}
331+
ad_connect ${ip_name}/s_axi_${j} ${ip_name}/xcvr/Quad${j}_AXI_LITE
332+
}
333+
}

‎projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl

Lines changed: 18 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -193,7 +193,7 @@ if {$ADI_PHY_SEL == 1} {
193193
}
194194
}
195195
} else {
196-
source $ad_hdl_dir/projects/ad9081_fmca_ebz/common/versal_transceiver.tcl
196+
source $ad_hdl_dir/library/xilinx/scripts/versal_xcvr_subsystem.tcl
197197

198198
set REF_CLK_RATE [ expr { [info exists ad_project_params(REF_CLK_RATE)] \
199199
? $ad_project_params(REF_CLK_RATE) : 375 } ]
@@ -209,7 +209,7 @@ if {$ADI_PHY_SEL == 1} {
209209

210210
switch $INTF_CFG {
211211
"RXTX" {
212-
create_versal_phy jesd204_phy_rxtx $JESD_MODE $RX_NUM_OF_LANES $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG
212+
create_versal_jesd_xcvr_subsystem jesd204_phy_rxtx $JESD_MODE $RX_NUM_OF_LANES $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG
213213
set rx_phy jesd204_phy_rxtx
214214
set tx_phy jesd204_phy_rxtx
215215
ad_connect ref_clk_q0 ${rx_phy}/GT_REFCLK
@@ -225,7 +225,7 @@ if {$ADI_PHY_SEL == 1} {
225225
ad_connect ${rx_phy}/tx_resetdone tx_resetdone
226226
}
227227
"RX" {
228-
create_versal_phy jesd204_phy_rx $JESD_MODE $RX_NUM_OF_LANES 0 $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG
228+
create_versal_jesd_xcvr_subsystem jesd204_phy_rx $JESD_MODE $RX_NUM_OF_LANES 0 $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG
229229
set rx_phy jesd204_phy_rx
230230
ad_connect ref_clk_q0 ${rx_phy}/GT_REFCLK
231231
ad_connect gt_reset ${rx_phy}/gtreset_in
@@ -237,7 +237,7 @@ if {$ADI_PHY_SEL == 1} {
237237
ad_connect ${rx_phy}/rx_resetdone rx_resetdone
238238
}
239239
"TX" {
240-
create_versal_phy jesd204_phy_tx $JESD_MODE 0 $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG
240+
create_versal_jesd_xcvr_subsystem jesd204_phy_tx $JESD_MODE 0 $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG
241241
set tx_phy jesd204_phy_tx
242242
ad_connect ref_clk_q0 ${tx_phy}/GT_REFCLK
243243
ad_connect gt_reset ${tx_phy}/gtreset_in
@@ -561,6 +561,20 @@ if {$INTF_CFG != "RX"} {
561561
ad_cpu_interrupt ps-10 mb-15 axi_mxfe_tx_jesd/irq
562562
}
563563

564+
# Connect PHY Quads to CPU
565+
if {!$ADI_PHY_SEL} {
566+
for {set i 0} {$i < $num_quads} {incr i} {
567+
set addr [expr 0x44a60000 + $i * 0x100000]
568+
if {$INTF_CFG == "RXTX"} {
569+
ad_cpu_interconnect $addr $rx_phy s_axi_${i}
570+
} elseif {$INTF_CFG == "RX"} {
571+
ad_cpu_interconnect $addr $rx_phy s_axi_${i}
572+
} elseif {$INTF_CFG == "TX"} {
573+
ad_cpu_interconnect $addr $rx_phy s_axi_${i}
574+
}
575+
}
576+
}
577+
564578
# Dummy outputs for unused lanes
565579
if {$ADI_PHY_SEL == 1} {
566580
if {$INTF_CFG != "TX"} {

‎projects/ad9081_fmca_ebz/vck190/Makefile

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ M_DEPS += ../../common/xilinx/adcfifo_bd.tcl
1414
M_DEPS += ../../common/vmk180/vmk180_system_bd.tcl
1515
M_DEPS += ../../common/vck190/vck190_system_constr.xdc
1616
M_DEPS += ../../common/vck190/vck190_system_bd.tcl
17-
M_DEPS += ../../ad9081_fmca_ebz/common/versal_transceiver.tcl
17+
M_DEPS += ../../../library/xilinx/scripts/versal_xcvr_subsystem.tcl
1818
M_DEPS += ../../ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
1919
M_DEPS += ../../../library/util_hbm/scripts/adi_util_hbm.tcl
2020
M_DEPS += ../../../library/util_cdc/sync_bits.v

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